1. Field of the Invention
This invention relates generally to the test and debug of multiple processors on a chip and, more particularly to the coupling of the test access ports (TAPs) associated with each processor to an external test and debug unit. The invention is specifically directed toward the test and debug of processor/cores having advanced power management.
2. Background of the Invention
Today's digital signal processors, microprocessor, and complex logic cores facilitate test via a limited pin interface called the JTAG interface. This interface conforms to the IEEE 1149.1 Test Access Port (TAP) protocol and requirements. Modern processor units often use the JTAG interface to provide access to in-circuit emulation (ICE) logic in order to facilitate debug of an embedded processor or logic system-on-a-chip designs. The processor unit often has multiple processors/cores, each processor/core having its own TAP.
The IEEE1149.1 specification has two ways in which multiple TAPs can be connected together. In the parallel configuration, a single TDI (test data in) input signal is connected to the TDI input of each TAP in the system. Similarly, the TDO (test data out) output signals from all of the processors/cores are wired together. A separate TMS control signal for each TAP is used to drive each TAP state independently. The controller assures that only one TAP at a time is put into a state in which it responds to the TDI input signals and transmits the TDO output signals.
The problem with a parallel configuration is that each TAP requires its own TMS control signal. On a system-on-a-chip with multiple processor/cores, this configuration would require several pins on the device. In addition, each of these pins would need to be coupled to a JTAG controller. This coupling would require additional signals on the processor unit board and the connector to the JTAG controller. This solution to the problem of multiple TAPS is not conveniently scalable. Since only one TAP can drive its TDO output at the same time, the parallel solution also does not facilitate co-emulation in which multiple TAPs need to be driven through the TAP state machine at the same time.
With the parallel configuration, one or more TAPs can be turned off or un-powered while preserving the ability to performs scans to active TAPs. However, once a TAP becomes inactive, there is no way for a controller to wakeup the module and re-enable scans.
The series configuration is the more common configuration for connecting multiple TAPS. This configuration requires that all TAPs be clocked with the same clock and the serial output of one TAP is used as the serial input to the next TAP in the system. This configuration supports both debug and test procedures.
There are several problems with the series test configuration. First, if the power is removed from one TAP in the series, then the controller will be unable to shift data into and out of any TAP linked in series with the un-powered TAP. Once a TAP has been un-powered, the scan controller is not able to wakeup the sleeping module. The second problem is that all TAPs must be clocked at the same frequency. Consequently, the maximum clock frequency is limited by the slowest component in the system. Synthesizable ARM processors from ARM Ltd exacerbate this problem since the JTAG TCK (test clock) clock signal must be synchronized with the ARM processor functional clock. This synchronized TCK signal, called the RTCK signal, must be used as the TCK signal for all other components linked in series with the ARM processor. Therefore, if the ARM clock is running at a slow frequency or is turned off, scanning through any of the TAPs in series with this core is not possible.
Another problem with the series configuration of TAPs is that to access one particular TAP, the controller must scan through all of the TAPs in the series. This feature makes scaling difficult. Systems or even systems-on-a-chip may have hundreds of processors. This complexity leads to a scan path that is thousands of bits long. A long scan path significantly slows debug of a selected processor core.
The series configuration also presents problems for production testing. Typically, the test vectors used in a production test are written for a single TAP. The test harness does not have an automated method to understand that other TAPs may precede or follow the TAP under test in the JTAG series. For each system, these test vectors must be rewritten to accommodate several TAPs in series.
In order to protect confidential information being processed on an embedded device, some devices are equipped with security features to block viewing of some data. Security features on a system may also be used to protect intellectual property, such as algorithms, drivers, or other software. Because debug procedures use the TAP on a processor to access ICE logic, security logic often disables the TAP on the protected core. In past designs, the TAP was disabled by gating the TCLK signal, which is the TAP clock signal.
Gating the TCLK signals presents several problems. First, gating the TCLK signal at the device level blocks debug and test procedures access to all TAPs and hence all processor/cores to in the system. This unsophisticated technique does not allow for visibility in the protected system while blocking visibility into other systems. Even if the TCLK signal was gated closer to the processor/core's TAP, this implementation would not help because the TAPs are connected in series. For the shifting through the series TAPs to be implemented, the TCLK signal must be enabled to all TAPs in the chain. The second problem is that blocking visibility into the system is in direct conflict with the needs of debug procedures that seek to give full visibility into the system. A method is needed to selectively and dynamically enable or disable access to all TAPs in a system.
Referring to FIG. 1, the configuration for testing a plurality of processor/cores 11-1N fabricated on a circuit board 1 according to the prior art is shown. Processor/cores 11-1N each includes a Test Access Port (TAP) unit 111-11N, respectively. A host processing unit 3, the apparatus that controls the testing of the processor/cores 11-1N, exchanges signals with an emulation unit 2. The emulation unit 2 formats the signals received from the host processing unit and applies the resulting signals to TAP units 11-1N. Each TAP unit 11-1N receives the TMS signal, the TCLK signal and the TRST signal. With respect to the TDI and TDO signals, the TAP units are coupled in series, the TDI signal being applied to the first TAP unit 11 in the series and the TDO signal being received from the last TAP unit 1N in the series.
Referring to FIG. 2, a block diagram of a TAP unit 20 according to the prior art is shown. The TAP unit 20 includes a state machine 21. The state machine, in response to the TMS signal, the TRST signal, and the TCLK signal generates control signals that control the sequencing and activity of the TAP unit 21. The TDI signal is applied to the switch unit 23. Switch 23 directs the TDI signals to the IR register 25 or to one of the DR registers 26-2N. The output signals of the registers are applied to the multiplexer 24, the output of the multiplexer 24 being the TDO signal. When the TDI is applied to the IR register 25, the contents of the IR register are applied to a logic unit 22. The logic unit 22 provides control signals that specify a test and debug activity.
The operation of the TAP unit 20 can be summarized as possible. A value is entered in the IR register 25. In response to the value, an activity is implemented by control signals generated by the logic unit 22. This result of a value in the IR register can be a transfer of a value from the DR register to a register in the processor/core result or can result in the transfer of a value in a processor/core register to a DR register. One predetermined value in the IR register 25 results in a logic “1” being set in the bit-by-pass register 29. Thus, in the example of a plurality of TAP units, a string of logic signals entered in all the IR registers and synchronized by the state machine, can short circuit one or more designated TAP units by setting the logic “1” in the by-pass bit register. When the contents of a string of DR registers in the TAP unit sequence is read out, the designated by-pass bit registers provide only a logic “1” output, in essence, providing a short circuit for the test and debug activity for the processor/core associated a designated tap register.
One of the problems that can arise in the test and debug of processor/cores having advanced power management systems is the change of power, either by slowing the clock in all of parts of the processor/core or by changing the power in all or parts of the processor/core. This change in power can result in a processor/core that can not be tested by the test and debug unit.
A need has therefore been felt for apparatus and an associated method having the feature of improving test and debug procedures. It is a more particular object of the apparatus and associated method to permit selective testing of a number of a plurality of processor. It is yet a further object of the apparatus and associated method to activate the selected processor/cores using JTAG test and debug procedures. It is a still further feature of the apparatus and associated method to provide a technique for determining the status of selected processor/core parameters for certain processor/cores. It is more particular feature of the apparatus and associated method to provide an interface unit between the test and debug apparatus and a plurality of processor/cores that can facilitate the test and debug procedures. It is a still further particular feature of the apparatus and associated method to provide an interface unit that includes a TAP unit. It is yet another particular feature of the apparatus and associated method to provide a status registers providing the status of the plurality of processor/cores under test. It is yet another feature of the apparatus and associated method to permit the uninterrupted test and debug of a processor/core having an advanced power management system.